ONE Lab would like to congratulate Eng. Islam Osama (ONE Lab former Master student) on his accepted journal paper at World Scientific Journal of Circuits, Systems, and Computers (JCSC) titled “ Functional Verification of Dynamic Partial Reconfiguration for Software-Defined Radio”. The paper Abstract is below:
Dynamic Partial Reconfiguration (DPR) on Field Programmable Gate Arrays (FPGAs) allows reconfiguration of some of the logic at runtime while the rest of the logic keeps operating. This feature allows the designers to build complex systems such as Software Defined Radio (SDR) in a reasonable area. New issues can arise due to usage of DPR technique such as guaranteeing proper connections for the ports of the Reconfigurable Modules (RMs) which share the same Reconfigurable Region (RR) on the FPGA, waiting for running computations on a module before reconfiguring it, isolation of the reconfigurable modules during the reconfiguration process, and initialization of the reconfigurable module after the reconfiguration process is done. Also, the Clock Domain Crossing (CDC) verification of the dynamically reconfigurable systems is a complicated task due to the need to verify all the modes of the designs, and the lack of Computer Aided Design (CAD) tools support for DRS designs. This article summarizes our previous work to address these verification challenges for Dynamic Partial Reconfiguration (DPR). The approaches are demonstrated on a Software-Defined Radio (SDR) system to show the effectiveness of applying these approaches in the design cycle.
