On May 05, 2021, Eng. Heba Elhosary (Current ONE Lab Master student at the German University in Cairo (GUC)), Eng. Michael Hany (Current ONE Lab Master student at Cairo University and Former ONE Lab Research Assistant – Currently with ICpedia), Eng. Mohamed Adel (Former ONE Lab Master student at Cairo University and Research Assistant – Currently at the University of Toronto – Canada), and Eng. Khaled Helal (Former ONE Lab Master student at Cairo University and Research Assistant – Currently at the University of British Columbia – Canada) have an accepted journal paper at IEEE Access journal titled “Hardware Acceleration of High Sensitivity Power-Aware Epileptic Seizure Detection System Using Dynamic Partial Reconfiguration“. The paper is a collaboration between Cairo University, Zewail City of Science and Technology, German University in Cairo (GUC), King Abdullah University of Science and Technology (KAUST), and TU Darmstadt.
In this paper, a high-sensitivity low-cost power-aware Support Vector Machine (SVM) training and classification based system, is hardware implemented for a neural seizure detection application. The training accelerator algorithm, adopted in this work, is the sequential minimal optimization (SMO). System blocks are implemented to achieve the best trade-off between sensitivity and the consumption of area and power. The proposed seizure detection system achieves 98.38% sensitivity when tested with the implemented linear kernel classifier. The system is implemented on different platforms: such as Field Programmable Gate Array (FPGA) Xilinx Virtex-7 board and Application Specific Integrated Circuit (ASIC) using hardware-calibrated UMC 65nm CMOS technology. A power consumption evaluation is performed on both the ASIC and FPGA platforms showing that the ASIC power consumption is lower by at least 65% when compared with the FPGA counterpart. A power-aware system is implemented with FPGAs by the adoption of the Dynamic Partial Reconfiguration (DPR) technique that allows the dynamic operation of the system based on power level available to the system at the expense of degradation of the system accuracy. The proposed system exploits the advantages of DPR technology in FPGAs to switch between two proposed designs providing a decrease of 64% in power consumption.
